k6r4016c1a-c, k6r4016c1a-e, k6r4016c1a-i cmos sram preliminary rev 2.1 - 1 - december 1998 document title 256kx16 bit high speed static ram(5v operating), revolutionary pin out. operated at commercial, extended and industrial temperature ranges. revision history the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to c hange the specifications. samsung electronics will evaluate and reply to your requests and questions on the parameters of this device. if you have any ques- tions, please contact the samsung branch office near your office, call or contact headquarters. rev no. rev. 0.0 rev. 0.5 rev. 1.0 rev.2.0 rev.2.1 remark design target preliminary final final final history initial release with design target. release to preliminary data sheet. 0.1. replace design target to preliminary. 0.2. delete 12ns part but add 17ns part. 0.3. relax d.c and a.c parameters and insert new parameter(icc 1 ) with the test condition. 0.3.1. insert icc 1 parameter with the test condition as address is increased with binary count. 0.3.2. relax d.c and a.c parameters. release to final data sheet. 1.1. delete preliminary. 1.2. delete icc1 parameter with the test condition. 1.3. update d.c parameters. 1.4. add the test condition for v oh1 with vcc=5v 5% at 25 c. 1.5. add timing diagram to define t wp1 as 2( timing wave form of write cycle( oe =low fixed) 2 . 2.1 add extended and industrial temperature range parts. add 44-tsop2 package. items previous spec. (15/ - /20ns part) relaxed spec. (15/17/20ns part) icc 250/ - /240ma 280/275/270ma t cw 10/ - /12ns 12/13/14ns t aw 10/ - /12ns 12/13/14ns t wp ( oe =h) 10/ - /12ns 12/13/14ns t wp1 ( oe =l) 12/ - /14ns 15/17/20ns t dw 7/ - /9ns 8/ 9/10ns items previous spec. (15/17/20ns part) updated spec. (15/17/20ns part) icc 280/275/270ma 210/205/200ma draft data jun. 14th, 1996 sep. 16th, 1996 jun. 5th, 1997 feb. 25th, 1998 dec. 14th, 1998
k6r4016c1a-c, k6r4016c1a-e, k6r4016c1a-i cmos sram preliminary rev 2.1 - 2 - december 1998 pin function pin name pin function a 0 - a 17 address inputs we write enable cs chip select oe output enable lb lower-byte control(i/o 1 ~i/o 8 ) ub upper-byte control(i/o 9 ~i/o 16 ) i/o 1 ~ i/o 16 data inputs/outputs v cc power(+5.0v) v ss ground n.c no connection 256k x 16 bit high-speed cmos static ram the k6r4016c1a is a 4,194,304-bit high-speed static ran- dom access memory organized as 262,144 words by 16 bits. the k6r4016c1a uses 16 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. also it allows that lower and upper byte access by data byte control( ub , lb ). the device is fabri- cated using samsung s advanced cmos process and designed for high-speed circuit technology. it is particularly well suited for use in high-density high-speed system applications. the k6r4016c1a is packaged in a 400mil 44-pin plastic soj or tsop(ii) forward. general description features ? fast access time 15, 17, 20ns(max.) ? low power dissipation standby (ttl) : 50ma(max.) (cmos) : 10ma(max.) operating k6r4016c1a-15 : 210ma(max.) k6r4016c1a-17 : 205ma(max.) k6r4016c1a-20 : 200ma(max.) ? single 5.0v 10% power supply ? ttl compatible inputs and outputs ? i/o compatible with 3.3v devices ? fully static operation - no clock or refresh required ? three state outputs ? center power/ground pin configuration ? data byte control ; lb : i/o 1 ~ i/o 8, ub : i/o 9 ~ i/o 16 ? standard pin configuration k6r4016c1a-j : 44-soj-400 k6r4016c1a-t : 44-tsop2-400bf clk gen. i/o 1 ~i/o 8 oe ub cs pin configuration (top view) soj/ functional block diagram r o w s e l e c t data cont. column select clk gen. pre-charge circuit memory array 1024 rows 256x16 columns i/o circuit & 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a 17 a 16 a 15 oe ub lb i/o 16 i/o 15 i/o 14 i/o 13 vss vcc i/o 12 i/o 11 i/o 10 i/o 9 n.c a 14 a 13 a 12 a 11 a 10 a 0 a 1 a 2 a 3 a 4 cs i/o 1 i/o 2 i/o 3 i/o 4 vcc vss i/o 5 i/o 6 i/o 7 i/o 8 we a 5 a 6 a 7 a 8 a 9 i/o 9 ~i/o 16 data cont. we lb 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a 10 a 12 a 14 a 16 a 11 a 13 a 15 a 17 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 k6r4016c1a-c15/c17/c20 commercial temp. k6r4016c1a-e15/e17/e20 extended temp. k6r4016c1a-i15/i17/i20 industrial temp. ordering information a 9 tsop2
k6r4016c1a-c, k6r4016c1a-e, k6r4016c1a-i cmos sram preliminary rev 2.1 - 3 - december 1998 recommended dc operating conditions* (t a =0 to 70 c) * the above parameters are also guaranteed at extended and industrial temperature ranges. ** v il (min) = -2.0v a.c(pulse width 10ns) for i 20ma. *** v ih (max) = v cc + 2.0v a.c (pulse width 10ns) for i 20ma. parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v ground v ss 0 0 0 v input high voltage v ih 2.2 - v cc + 0.5** v input low voltage v il -0.5* - 0.8 v dc and operating characteristics* (t a =0 to 70 c, vcc=5.0v 10%, unless otherwise specified) * the above parameters are also guaranteed at extended and industrial temperature ranges. parameter symbol test conditions min max unit input leakage current i li v in =v ss to v cc -2 2 m a output leakage current i lo cs =v ih or oe =v ih or we =v il v out = v ss to v cc -2 2 m a operating current i cc min. cycle, 100% duty cs =v il, v in =v ih or v il, i out =0ma 15ns - 210 ma 17ns - 205 20ns - 200 standby current i sb min. cycle, cs =v ih - 50 ma i sb1 f=0mhz, cs 3 v cc -0.2v, v in 3 v cc -0.2v or v in 0.2v - 10 ma output low voltage level v ol i ol =8ma - 0.4 v output high voltage level v oh i oh =-4ma 2.4 - v capacitance* (t a =25 c, f=1.0mhz) * capacitance is sampled and not 100% tested. item symbol test conditions min max unit input/output capacitance c i/o v i/o =0v - 8 pf input capacitance c in v in =0v - 7 pf absolute maximum ratings* * stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress r ating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this spec ification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v in , v out -0.5 to 7.0 v voltage on v cc supply relative to v ss v cc -0.5 to 7.0 v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature commercial t a 0 to 70 c extended t a -25 to 85 c industrial t a -40 to 85 c
k6r4016c1a-c, k6r4016c1a-e, k6r4016c1a-i cmos sram preliminary rev 2.1 - 4 - december 1998 test conditions* * the above parameters are also guaranteed at extended and industrial temperature ranges. parameter value input pulse levels 0v to 3v input rise and fall times 3ns input and output timing reference levels 1.5v output loads see below ac characteristics (t a =0 to 70 c, v cc =5.0v 10%, unless otherwise noted.) output loads(a) output loads(b) d out 5pf* 480 w 255 w for t hz , t lz , t whz , t ow , t olz & t ohz +5.0v d out 30pf* 480 w 255 w +5.0v * including scope and jig capacitance read cycle* * the above parameters are also guaranteed at extended and industrial temperature ranges. parameter symbol k6r4016c1a-15 k6r4016c1a-17 k6r4016c1a-20 unit min max min max min max read cycle time t rc 15 - 17 - 20 - ns address access time t aa - 15 - 17 - 20 ns chip select to output t co - 15 - 17 - 20 ns output enable to valid output t oe - 7 - 8 - 9 ns ub , lb access time t ba - 7 - 8 - 9 ns chip enable to low-z output t lz 3 - 3 - 3 - ns output enable to low-z output t olz 0 - 0 - 0 - ns ub , lb enable to low-z output t blz 0 - 0 - 0 - ns chip disable to high-z output t hz 0 7 0 8 0 9 ns output disable to high-z output t ohz 0 7 0 8 0 9 ns ub , lb disable to high-z output t bhz 0 7 0 8 0 9 ns output hold from address change t oh 3 - 3 - 3 - ns
k6r4016c1a-c, k6r4016c1a-e, k6r4016c1a-i cmos sram preliminary rev 2.1 - 5 - december 1998 write cycle* * the above parameters are also guaranteed at extended and industrial temperature ranges. parameter symbol k6r4016c1a-15 k6r4016c1a-17 k6r4016c1a-20 unit min max min max min max write cycle time t wc 15 - 17 - 20 - ns chip select to end of write t cw 12 - 13 - 14 - ns address set-up time t as 0 - 0 - 0 - ns address valid to end of write t aw 12 - 13 - 14 - ns write pulse width( oe high) t wp 12 - 13 - 14 - ns write pulse width( oe low) t wp1 15 - 17 - 20 - ns ub , lb valid to end of write t bw 12 - 13 - 14 - ns write recovery time t wr 0 - 0 - 0 - ns write to output high-z t whz 0 7 0 8 0 9 ns data to write time overlap t dw 8 - 9 - 10 - ns data hold from write time t dh 0 - 0 - 0 - ns end write to output low-z t ow 3 - 3 - 3 - ns address data out previous valid data valid data timming diagrams timing waveform of read cycle(1) (address controlled , cs = oe =v il , we =v ih , ub , lb =v il ) t aa t rc t oh
k6r4016c1a-c, k6r4016c1a-e, k6r4016c1a-i cmos sram preliminary rev 2.1 - 6 - december 1998 notes (read cycle) 1. we is high for read cycle. 2. all read cycle timing is referenced from the last valid address to the first transition address. 3. t hz and t ohz are defined as the time at which the outputs achieve the open circuit condition and are not referenced to v oh or v ol levels. 4. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device. 5. transition is measured 200mv from steady state voltage with load(b). this parameter is sampled and not 100% tested. 6. device is continuously selected with cs =v il. 7. address valid prior to coincident with cs transition low. 8. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e. timing waveform of write cycle(1) ( oe clock) address cs ub , lb we data in data out t wc t cw(3) t bw t wp(2) t as(4) t dh t dw t ohz(6) high-z high-z valid data oe t aw t wr(5) timing waveform of read cycle(2) ( we =v ih ) valid data high-z t rc cs address ub , lb oe data out t hz(3,4,5) t aa t co t ba t oe t olz t lz(4,5) t oh t ohz t bhz(3,4,5) t blz(4,5)
k6r4016c1a-c, k6r4016c1a-e, k6r4016c1a-i cmos sram preliminary rev 2.1 - 7 - december 1998 timing waveform of write cycle(3) ( cs =controlled) address cs t aw t dw t dh valid data we data in data out high-z high-z(8) ub , lb t cw(3) t wp(2) t as(4) t wc t wr(5) high-z high-z t lz t whz(6) t bw timing waveform of write cycle(2) ( oe =low fixed) address cs ub , lb we data in data out t wc t cw(3) t bw t wp1(2) t dh t dw t wr(5) t as(4) t ow t whz(6) (10) (9) high-z valid data t aw high-z
k6r4016c1a-c, k6r4016c1a-e, k6r4016c1a-i cmos sram preliminary rev 2.1 - 8 - december 1998 functional description * x means don t care. cs we oe lb ub mode i/o pin supply current i/o 1 ~i/o 8 i/o 9 ~i/o 16 h x x* x x not select high-z high-z i sb , i sb1 l h h x x output disable high-z high-z i cc l x x h h l h l l h read d out high-z i cc h l high-z d out l l d out d out l l x l h write d in high-z i cc h l high-z d in l l d in d in address cs valid data ub , lb we data in data out timing waveform of write cycle(4) ( ub , lb controlled) t wc t cw(3) t bw t wp(2) t dh t dw t wr(5) t aw t as(4) high-z high-z(8) t blz t whz(6) high-z notes (write cycle) 1. all write cycle timing is referenced from the last valid address to the first transition address. 2. a write occurs during the overlap of a low cs , we , lb and ub . a write begins at the latest transition cs going low and we going low; a write ends at the earliest transition cs going high or we going high. t wp is measured from the beginning of write to the end of write. 3. t cw is measured from the later of cs going low to end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs or we going high. 6. if oe , cs and we are in the read mode during this period, the i/o pins are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7. for common i/o applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e. 8. if cs goes low simultaneously with we going or after we going low, the outputs remain high impedance state. 9. dout is the read data of the new address. 10. when cs is low: i/o pins are in the output state. the input signals in the opposite phase leading to the output should not be applied.
k6r4016c1a-c, k6r4016c1a-e, k6r4016c1a-i cmos sram preliminary rev 2.1 - 9 - december 1998 #1 44-soj-400 #44 25.58 0.12 1.125 0.005 max 28.98 1.141 max 0.148 3.76 1.19 ( ) 0.047 1.27 ( ) 0.050 0.95 ( ) 0.0375 + 0.10 0.43 - 0.05 + 0.004 0.017 - 0.002 + 0.10 0.71 - 0.05 + 0.004 0.028 - 0.002 1.27 0.050 1 0 . 1 6 0 . 4 0 0 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 9.40 0.25 0.370 0.010 min 0.69 0.027 #22 #23 0.004 0.10 max 11.18 0.12 0.440 0.005 package dimensions units:millimeters/inches 1.00 0.10 0.039 0.004 44-tsop2-400bf 0.002 #1 0.05 #22 #23 0.30 0.012 0.80 0.0315 min 0.047 1.20 max 0.741 18.81 max 18.41 0.10 0.725 0.004 11.76 0.20 0.463 0.008 + 0.075 - 0.035 0.50 + 0.003 - 0.001 0.125 0.005 0.020 1 0 . 1 6 0 . 4 0 0 0.10 0.004 0~8 0.45 ~0.75 0.018 ~ 0.030 ( ) 0.805 0.032 ( ) max units:millimeters/inches #44 0.25 0.010 typ + 0.10 - 0.05 + 0.004 - 0.002
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